The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which provides chip selection means. The semiconductor memory device of the present invention is in the form of a ROM, an EPROM, a PROM, an EAROM or a RAM.
In the system which uses a plurality of memory chips, it is necessary to select the desired memory chip by means of address signal supplied to the system.
In the prior art systems illustrated in FIGS. 1A and 1B, each of the chips CH-1, CH-2, CH-3 and CH-4 provides a chip selection terminal CS or chip selection terminals CS.sub.1 (CS.sub.1) and CS.sub.2 (CS.sub.2). The chips of FIG. 1B are of the Mask ROM type. The chip selection logic is determined in the wafer processing stage. The chip selection signal SEL which occupies the higher bit portions of the address signal ADR is supplied to the external decoder circuit in FIG. 1A and the chip selection terminals CS.sub.1 (CS.sub.1) and CS.sub.2 (CS.sub.2) in FIG. 1B.
The disadvantage of the prior art system of FIG. 1A is that an external decoder circuit DEC is required to generate from signal SEL the signals to select the desired chip.
The disadvantage of the prior art system of FIG. 1B is that it is impossible to change the select condition of the signals applied to the chip selection terminals CS.sub.1 (CS.sub.1) and CS.sub.2 (CS.sub.2), once they are selected at wafer processing.
The present invention eliminates the disadvantages in the prior art semiconductor memory systems described above.